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Features
* * * * * * * * * *
Low Voltage Operation - 2.7V Read - 5V Program/Erase Fast Read Access Time - 120 ns Internal Erase/Program Control Sector Architecture - One 8K Words (16K bytes) Boot Block with Programming Lockout - Two 8K Words (16K bytes) Parameter Blocks - One 232K Words (464K bytes) Main Memory Array Block Fast Sector Erase Time - 10 seconds Word-By-Word Programming - 10 s/Word Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation - 25 mA Active Current - 50 A CMOS Standby Current Typical 10,000 Write Cycles
Description
The AT49BV4096 and AT49LV4096 are 3-volt, 4-megabit Flash Memories organized as 256K words of 16 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 120 ns with power dissipation of just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than 50 A. To allow for simple in-system reprogrammability, the AT49BV4096/LV4096 does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus
4-Megabit (256K x 16) 3-volt Only CMOS Flash Memory AT49BV4096 AT49LV4096 Preliminary
AT49BV4096/LV4096
Pin Configurations
Pin Name A0 - A17 CE OE WE RESET VPP I/O0 - I/O15 NC Function Addresses Chip Enable Output Enable Write Enable Reset Program/Erase Power Supply Data Inputs/Outputs No Connect
VPP NC A17 A7 A6 A5 A4 A3 A2 A1 A0
48 46 44 42 40 38 36 34 32 30 28 26 25 47 45 43 41 39 37 35 33 31 29 27 NC I/O15 I/O14 I/O13 I/O12 VCC I/O3 I/O2 I/O1 I/O0 GND A0 CE A16 GND I/O7 I/O6 I/O5 I/O4 I/O11 I/O10 I/O9 I/O8 OE
(continued)
SOIC (SOP)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 NC GND I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC
TSOP Top View
Type 1
A15 A13 A11 A9 A14 A12 A10 A8 4 6 8 10 12 14 16 18 20 22 24 1 3 5 7 9 11 13 15 17 19 21 23 2
NC NC WE RESET VPP NC NC NC A17 A7 A6 A5 A4 A3 A2 A1
CE GND OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11
0874A-5/97
contention. Reprogramming the AT49BV4096/LV4096 is performed by first erasing a block of data and then programming on a word-by-word basis. The device is erased by executing the erase command sequence; the device internally controls the erase operation. The memory is divided into three blocks for erase operations. There are two 8K word parameter block sections and one sector consisting of the boot block and the main memory array block. The AT49BV4096/LV4096 is programmed on a word-by-word basis. The device has the capability to protect the data in the boot block; this feature is enabled by a command se-
quence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 3.6 volts or less are used. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K word boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed. During a chip erase, sector erase, or word programming, the VPP pin must be at 5V 10%.
Block Diagram
Device Operation
READ: The AT49BV4096/LV4096 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. 2 RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the Read or Standby mode, depending upon the state of the control inputs. By applying a 12V 0.5V input signal to the RESET pin the boot block array can be reprogrammed even if the boot block program lockout feature has been enabled (see Boot Block Programming Lockout Override section). ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands. CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erease the chip is tEC.
AT49BV/LV4096
AT49BV/LV4096
If the boot block lockout has been enabled, the Chip Erase will not erase the data in the boot block; it will erase the main memory block and the parameter blocks only. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into three sectors that can be individually erased. There are two 8K word parameter block sections and one sector consisting of the boot block and the main memory array block. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together (from the same sector erase command). Once the boot region has been protected, only the main memory array sector will erase when its sector erase command is issued. WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical "0") on a word-byword basis. Programming is accomplished via the internal device command register and is a 4 bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset happens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been enabled and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 0.5 volts. By doing this protected boot block data can be altered through a chip erase, sector erase or word programming. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV4096/LV4096 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. DATA polling may begin at any time during the program cycle. TOGGLE BIT: I n a d d i t i o n t o DATA p o l l i n g t h e AT49BV4096/LV4096 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV4096/LV4096 in the following ways: (a) VCC 3
sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power on delay: once VCC h a s reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE, and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
Command Definition (in Hex) (1)
Command Bus Sequence Cycles Read Chip Erase 1 6 6 4 6 3 3 1
1st Bus Cycle
Addr Addr 5555 5555 5555 5555 5555 5555 xxxx Data DOUT AA AA AA AA AA AA F0
2nd Bus Cycle
Addr 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA Data 55 55 55 55 55 55
3rd Bus Cycle
Addr 5555 5555 5555 5555 5555 5555 Data 80 80 A0 80 90 F0
4th Bus Cycle
Addr 5555 5555 Addr 5555 Data AA AA DIN AA
5th Bus Cycle
Addr 2AAA 2AAA Data 55 55
6th Bus Cycle
Addr 5555 SA (4, 5) Data 10 30
Sector Erase
Word Program Boot Block (2) Lockout Product ID Entry Product ID (3) Exit Product ID (3) Exit
2AAA
55
5555
40
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) 2. The 8K word boot sector has the address range 00000H to 01FFFH. 3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses: SA = 03XXX for PARAMETER BLOCK 1 SA = 05XXX for PARAMETER BLOCK 2 SA = 1FXXX for MAIN MEMORY ARRAY 5. When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase
Absolute Maximum Ratings*
Temperature Under Bias................. -55C to +125C Storage Temperature...................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ................... -0.6V to +6.25V All Output Voltages with Respect to Ground .............-0.6V to V CC + 0.6V Voltage on OE with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT49BV/LV4096
AT49BV/LV4096
DC and AC Operating Range
AT49LV4096-12 Operating Temperature (Case) VCC Power Supply Com. Ind. AT49LV4096 AT49BV4096 0C - 70C -40C - 85C 3.0V to 3.6V N/A AT49BV/LV4096-15 0C - 70C -40C - 85C 3.0V to 3.6V 2.7V to 3.6V AT49BV/LV4096-20 0C - 70C -40C - 85C 3.0V to 3.6V 2.7V to 3.6V
Operating Modes
Mode Read Program/ Erase(2) Standby/Program Inhibit Program Inhibit Program Inhibit Output Disable Reset Product Identification Hardware Software (5)
Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V 0.5V.
CE VIL VIL VIH X X X X
OE VIL VIH X(1) X VIL VIH X
WE VIH VIL X VIH X X X
RESET VIH VIH VIH VIH VIH VIH VIL
VPP X 5V 10% X VIL VIL X X
Ai Ai Ai X
I/O DOUT DIN High Z
High Z
X
High Z
VIL
VIL
VIH
VIH
A1 - A17 = VIL, A9 = VH,(3) A0 = VIL A1 - A17 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL, A1 - A17 = VIL A0 = VIH, A1 - A17 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
VIH
4. Manufacturer Code: 1FH, Device Code: 92H 5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH
Note:
(1)
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA
Min
Max 10 10 50 1 25 0.8
Units A A A mA mA V V V V
2.0 IOL = 2.1 mA IOH = -400 A 2.4 .45
1. In the erase mode, ICC is 50 mA.
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AC Read Characteristics
AT49LV4096-12 Symbol tACC tCE tOE tDF tOH
(1) (2) (3, 4)
AT49BV/LV4096-15 Min Max 150 150 0 0 0 100 50
AT49BV/LV4096-20 Min Max 200 200 0 0 0 100 50 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 120 120
0 0 0
50 30
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance (f = 1 MHz, T = 25C) (1)
Typ CIN COUT
Note:
Max 6 12
Units pF pF
Conditions VIN = 0V VOUT = 0V
4 8
1. This parameter is characterized and is not 100% tested.
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AT49BV/LV4096
AT49BV/LV4096
AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 10 100 0 0 200 100 10 200 Max Units ns ns ns ns ns ns ns ns
AC Word Load Waveforms
WE Controlled
CE Controlled
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Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Word Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 100 100 0 200 200 10 Min Typ 10 Max 50 Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP tWPH tBP
WE
tAS tAH
5555
tDH
2AAA 5555 ADDRESS
AO-A17
5555
tDS
DATA
AA
55
A0
INPUT DATA
AA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP tWPH
WE
tAS tAH
5555
tDH
2AAA 5555 5555 2AAA Note 2
AO-A17
tDS
tEC
55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 Note 3 WORD 5
DATA
AA WORD 0
Notes: 1. OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
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AT49BV/LV4096
AT49BV/LV4096
Data Polling Characteristics
Symbol tDH tOEH tOE tWR Parameter Data Hold Time OE Hold Time OE to Output Delay
(2) (1)
Min 10 10 0
Typ
Max
Units ns ns ns ns
Write Recovery Time
Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics
Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time
(1)
Min 10 10 150 0
Typ
Max
Units ns ns ns ns ns
OE to Output Delay (2) OE High Pulse Write Recovery Time
Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. (1, 2, 3)
Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary.
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Software Product (1) Identification Entry
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE (2, 3, 5)
Boot Block Lockout (1) Enable Algorithm
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA
Software Product (1, 6) Identification Exit
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE (4) OR LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE (4)
LOAD DATA 40 TO ADDRESS 5555
PAUSE 1 second
Notes for boot block lockout feature enable: 1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled.
Notes for software product identification: 1. Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A14 - A0 (Hex). 2. A1 - A17 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 92H 6. Either one of the Product ID Exit commands can be used.
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AT49BV/LV4096
AT49BV/LV4096
Ordering Information (1)
tACC (ns) 120 ICC (mA)
Active Standby
Ordering Code AT49LV4096-12RC AT49LV4096-12TC AT49LV4096-12RI AT49LV4096-12TI
Package 44R 48T 44R 48T 44R 48T 44R 48T 44R 48T 44R 48T 44R 48T 44R 48T 44R 48T 44R 48T
Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C)
25
0.05
150
25
0.05
AT49LV4096-15RC AT49LV4096-15TC AT49LV4096-15RI AT49LV4096-15TI
200
25
0.05
AT49LV4096-20RC AT49LV4096-20TC AT49LV4096-20RI AT49LV4096-20TI
150
25
0.05
AT49BV4096-15RC AT49BV4096-15TC AT49BV4096-15RI AT49BV4096-15TI
200
25
0.05
AT49BV4096-20RC AT49BV4096-20TC AT49BV4096-20RI AT49BV4096-20TI
Note:
1. The AT49BV4096/LV4096 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher address range should contact Atmel.
Package Type
44R 48T
44 Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP) 48 Lead, Thin Small Outline Package (TSOP)
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